Прогр.4.3

library ieee;

use ieee.std_logic_1164.all;

port(a,b:in bit_vector(7 downto 0);

entity add8 is

s:out bit_vector(7 downto 0);

c: out bit);

end add8;

architecture structural of add8 is

component add1

port(a1,b1:in BIT;c1,s1:out BIT);

end component;

component add11

port (c1,a2,b2:in BIT; c2,s2:out BIT);

end component;

signal c_in: bit_vector(6 downto 0);

begin

p0: add1

port map(a1=>a(0),b1=>b(0),c1=>c_in(0),s1=>s(0));

p1: add11

port map(c1=>c_in(0),a2=>a(1),b2=>b(1),c2=>c_in(1),s2=>s(1));

p2: add11

port map(c1=>c_in(1),a2=>a(2),b2=>b(2),c2=>c_in(2),s2=>s(2));

p3: add11

port map(c1=>c_in(2),a2=>a(3),b2=>b(3),c2=>c_in(3),s2=>s(3));

p4: add11

port map(c1=>c_in(3),a2=>a(4),b2=>b(4),c2=>c_in(4),s2=>s(4));

p5: add11

port map(c1=>c_in(4),a2=>a(5),b2=>b(5),c2=>c_in(5),s2=>s(5));

p6: add11

port map(c1=>c_in(5),a2=>a(6),b2=>b(6),c2=>c_in(6),s2=>s(6));

p7: add11

port map(c1=>c_in(6),a2=>a(7),b2=>b(7),c2=>c,s2=>s(7));

end structural;