Прогр.2.2

library ieee;

use ieee.std_logic_1164.all;

entity dec1 is

port(

adr_i: in bit_vector(1 downto 0);

en: in bit;

data_out: out bit_vector(3 downto 0)

);

end dec1;

architecture BBB of dec1 is

begin

process (adr_i)

begin

if (en = '1') then

data_out(0)<=(not(adr_i(0)))and(not(adr_i(1)));

data_out(1)<=(adr_i(0))and(not(adr_i(1)));

data_out(2)<=(not(adr_i(0)))and(adr_i(1));

data_out(3)<=(adr_i(0))and(adr_i(1));

elsif (en ='0') then

data_out(3 downto 0)<="0000";

end if;

end process;

end;

Лабораторная работа № 3.